ATxmega256A1

ATxmega256A1 特性

• High-performance, Low-power 8/16-bit AVR XMEGA Microcontroller
• Non-Volatile Program and Data Memories
  – 64K - 384K Bytes of In-System Self-Programmable Flash
  – 4K - 8K Bytes Boot Section with Independent Lock Bits
  – 2K - 4K Bytes EEPROM
  – 4K - 32K Bytes Internal SRAM
  External Bus Interface for up to 16M bytes SRAM
  External Bus Interface for up to 128M bit SDRAM
• Peripheral Features
  – Four-channel DMA Controller with support for external requests
  – Eight-channel Event System
  – Eight 16-bit Timer/Counters
  Four Timer/Counters with 4 Output Compare or Input Capture channels
  Four Timer/Counters with 2 Output Compare or Input Capture channels
  High-Resolution Extension on all Timer/Counters
  Advanced Waveform Extension on two Timer/Counters
  – Eight USARTs
  IrDA modulation/demodulation for one USART
  – Four Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
  – Four SPI (Serial Peripheral Interface) peripherals
  – AES and DES Crypto Engine
  – 16-bit Real Time Counter with separate Oscillator
  – Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
  – Two Two-channel, 12-bit, 1 Msps Digital to Analog Converters
  – Four Analog Comparators with Window compare function
  – External Interrupts on all General Purpose I/O pins
  – Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
  – Power-on Reset and Programmable Brown-out Detection
  – Internal and External Clock Options with PLL and Prescaler
  – Programmable Multi-level Interrupt Controller
  – Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
  – Advanced Programming, Test and Debugging Interfaces
  JTAG (IEEE 1149.1 Compliant) Interface for programming, test and debugging
  PDI (Program and Debug Interface) for programming and debugging
• I/O and Packages
  – 78 Programmable I/O Lines
  – 100 - lead TQFP
  – 100 - ball CBGA
• Operating Voltage
  – 1.6 – 3.6V
• Speed performance
  – 0 – 12 MHz @ 1.6 – 3.6V
  – 0 – 32 MHz @ 2.7 – 3.6V

ATxmega256A1 概述

The XMEGA A1 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR?enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the XMEGA A1 achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conventional
single-accumulator or CISC based microcontrollers.
The XMEGA A1 devices provides the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 78 general purpose
I/O lines, 16-bit Real Time Counter (RTC), eight flexible 16-bit Timer/Counters with compare
modes and PWM, eight USARTs, four Two Wire Serial Interfaces (TWIs), four Serial Peripheral
Interfaces (SPIs), AES and DES crypto engine, two 8-channel, 12-bit ADCs with optional differential
input with programmable gain, two 2-channel, 12-bit DACs, four analog comparators with
window mode, programmable Watchdog Timer with seperate Internal Oscillator, accurate internal
oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A1 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consumption.
In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock to each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The program
Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Application
Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A1 is a powerful
microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A1 devices is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, programmers, and
evaluation kits.

ATxmega256A1 訂購型號

ATxmega256A1 技術(shù)支持

1. ATMEL 愛特梅爾AVR 微控制器 ATxmega256A1 中文數(shù)據(jù)手冊DataSheet 下載. PDF
2. ATMEL 愛特梅爾AVR 微控制器ATxmega256A1 數(shù)據(jù)手冊DataSheet 下載. PDF
3. ATMEL 愛特梅爾半導(dǎo)體公司產(chǎn)品線. PDF (編號:Atmel Products)
4. Atmel 愛特梅爾AVR 微控制器簡介.PDF (編號:Tech AVR 000)MLF32
5. 面向新手的AVR開發(fā)工具,及基本知識.PDF(編號:Tech AVR 001)
6. 使用AVR 定時/計數(shù)器的PWM功能設(shè)計要點 .PDF (編號:Tech AVR 002)